Showing results 31 to 50 of 79
< previous
next >
| Issue Date | Title | Author(s) |
| 20-Jun-2021 | Estimating per-unit-length resistance parameter in emerging Copper-Graphene hybrid interconnects via prior knowledge based accelerated neural networks | Kumar, R.; Narayan, S. S. L.; Kumar, S.; Roy, S.; Kaushik, B. K.; Achar, R.; Sharma, R. |
| 26-Aug-2022 | Fast extraction of per-unit-length parameters of hybrid copper-graphene interconnects via generalized knowledge based machine learning | Kushwaha, S.; Attar, A.; Trinchero, R.; Canavero, F.; Sharma, R.; Roy, S. |
| 21-Nov-2016 | Finance growth nexus across Indian states: evidences from panel cointegration and causality tests | Sharma, R.; Bardhan, S. |
| 11-Oct-2021 | Finance growth nexus across indian states: evidences from panel cointegration and causality tests | Sharma, R.; Bardhan, S. |
| 24-Jun-2021 | First principle analysis of Li-Doped armchair graphene nanoribbons for nanoscale metal interconnect applications | Nishad, V. K.; Sharma, R. |
| 13-Jun-2021 | First principle analysis of os-passivated armchair graphene nanoribbons for nanoscale interconnects | Nishad, V. K.; Nishad, A. K.; Kaushik, B. K.; Sharma, R. |
| 1-Aug-2021 | First-principle analysis of transition metal edge-passivated armchair graphene nanoribbons for nanoscale interconnects | Nishad, V. K.; Nishad, A. K.; Kaushik, B. K.; Sharma, R. |
| 11-Dec-2019 | Foreword: special section on packaging and interconnects: cutting-edge solutions in modeling, design, and characterization—part I | Telescu, M.; Gu, X.; Sharma, R. |
| 11-Dec-2019 | Foreword: special section on packaging and Interconnects: cutting-edge solutions in modeling, design, and characterization—Part II | Telescu, M.; Gu, X.; Sharma, R. |
| 4-Oct-2021 | A high-k, metal gate vertical-slit FET for ultra-low power and high-speed applications | Kumar, S.; Kaur, S.; Sharma, R. |
| 22-Nov-2022 | High-speed interconnects: History, evolution, and the road ahead | Kumbhare, V.R.; Kumar, R.; Majumder, M.K.; Kumar, S.; Paltani, P.P.; Kaushik, B.K.; Sharma, R. |
| 3-Sep-2022 | The IEEE EPS packaging benchmark suite | Guo, F.; Aygun, K.; Dale Becker, W.; Talocia, S.G.; Hejase, J.A.; Wong, W.-W.; Zhou, T.; Barnes, H.; Peng, Z.; Pelger, A.; Sahouli, M.; Schutt-Aine, J.; Ling, F.; Griese, E.; Paladhi, P.R.; Sharma, R.; Pham, N.; Winkel, T.-M.; Fledell, E.; Hill, M.J.; Silva, B.; Hu, K.; Aronsson, J.; Liu, C.; Jeong, Y.; Yilmaz, A.E. |
| 23-Aug-2019 | Implications of on-chip single-source clocking on high-speed serial interfaces in network soc | Pandey, M.K.; Gupta, T.; Sharma, R. |
| 1-Sep-2021 | Investigating the role of interconnect surface roughness towards the design of poweraware network on chip | Kumar, S.; Sharma, R. |
| 1-Dec-2021 | Investigating the role of parasitic resistance in a class of nanoscale interconnects | Yousuf, S. Z.; Bhardwaj, A. K.; Sharma, R. |
| 13-Nov-2018 | Investigating the role of sidewall surface roughness on the performance of through silicon vias | Kumar, S.; Pathania, S.; Sharma, R. |
| 24-Oct-2021 | Knowledge-Based neural networks for fast design space exploration of hybrid Copper-Graphene On-Chip interconnect networks | Kumar, R.; Narayan, S. S. L.; Kumar, S.; Roy, S.; Kaushik, B. K.; Achar, R.; Sharma, R. |
| 23-Jun-2022 | Knowledge-based neural networks for fast design space exploration of Hybrid Copper-Graphene on-chip interconnect networks | Kumar, R.; Narayan, S.S.L.; Kumar, S.; Roy, S.; Kaushik, B.; Achar, R.; Sharma, R. |
| 30-Sep-2021 | Lithium-Intercalated graphene interconnects: prospects for On-Chip applications | Nishad, A. K.; Sharma, R. |
| 20-Dec-2022 | Low-overhead PUF based hardware security technique to prevent scan chain attacks for industry-standard DFT architecture | Chittoriya, S.; Shivdeep; Jha, K.K.; Das, D.M.; Sharma, R. |
