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Browsing by Author Pathania, S.

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Showing results 1 to 9 of 9
Issue DateTitleAuthor(s)
5-Dec-2019Analyzing crosstalk-induced effects in rough on-chip copper interconnectsPathania, S.; Kumar, S.; Sharma, R.
19-Mar-2020Crosstalk analysis for rough copper interconnects considering ternary logicPathania, S.; Kumar, S.; Sharma, R.
25-Aug-2022Design and performance benchmarking of dual gate flexible bilayer graphene FETsPathania, S.; Gupta, P.; Kumar, R.; Kumar, S.
13-Nov-2018Investigating the role of sidewall surface roughness on the performance of through silicon viasKumar, S.; Pathania, S.; Sharma, R.
12-Aug-2021Multiphysics approach using computational fluid dynamics for signal integrity analysis in high speed serial linksPathania, S.; Vasa, M.; Shrivastava, A.; Kumar, S.; Kumar, V.; Muthusamy, S.; Seema, P.K.; Mutnury, B.; Sharma, R.
24-Jun-2021Role of grain Size on the effective resistivity of Cu-Graphene hybrid interconnectsKumar, R.; Pathania, S.; Guglani, S.; Kumar, A.; Kumar, S.; Roy, S.; Kaushik, B. K.; Sharma, R.
31-Jan-2022Signal integrity analysis of high speed onchip and chip-to-chip copper interconnectsPathania, S.
19-Aug-2021Thermal impact on high speed PCB interconnectsPathania, S.; Vasa, M.; Mutnury, B.; Sharma, R.
22-Jun-2021Thermal sensitivity of dielectric materials in High-Speed designsPathania, S.; Mutnury, B.; Vasa, M.; Kumar, V.; Muthusamy, S.; Seema, P. K.; Sharma, R.
Showing results 1 to 9 of 9