Investigating the role of sidewall surface roughness on the performance of through silicon vias

Abstract

In this paper, we present the effect of sidewall roughness, formed by Bosch etching, on the performance of TSVs for frequencies up to 100GHz. Industry standard EM solvers, Ansys HFSS and Q3D extractor are used for our analysis. We present the effect of sidewall roughness on the RLC parasitics, delay, energy-delay product (EDP), insertion loss (S21) and return loss (S11) for broadband frequencies up to 100 GHz. Our results show that for chip level TSVs at 100 GHz and 72nm sidewall roughness, insertion loss increase by 7% and return loss decreases by 13% when compared to that of smooth TSVs. Similarly, for wafer level TSVs, insertion loss increases due to roughness. Resistance increases by 1.3X and 1.5X at 100 GHz for wafer level and chip level TSVs, respectively. Energy delay product (EDP) also increases by 1.3X and 1.56X at 100 GHz for wafer level and chip level TSVs, respectively, due to increase in resistive loss. Finally, we present the computational overhead occurred in EM simulations of TSVs with sidewall roughness.