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dc.contributor.authorPandey, M.K.-
dc.contributor.authorGupta, T.-
dc.contributor.authorSharma, R.-
dc.date.accessioned2019-08-23T09:07:37Z-
dc.date.available2019-08-23T09:07:37Z-
dc.date.issued2019-08-23-
dc.identifier.urihttp://localhost:8080/xmlui/handle/123456789/1314-
dc.description.abstractSingle-source clocking is important for networked SoC architectures. This article discusses the validation challenges related to on-chip single-source clocking due to the distributed clocking trends of recent SoCs and proposes a new low cost and no SoC re-spin solution. - Paul Bogdan, University of Southern California. © 2013 IEEE.en_US
dc.language.isoen_USen_US
dc.titleImplications of on-chip single-source clocking on high-speed serial interfaces in network socen_US
dc.typeArticleen_US
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