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DC Field | Value | Language |
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dc.contributor.author | Pandey, M.K. | - |
dc.contributor.author | Gupta, T. | - |
dc.contributor.author | Sharma, R. | - |
dc.date.accessioned | 2019-08-23T09:07:37Z | - |
dc.date.available | 2019-08-23T09:07:37Z | - |
dc.date.issued | 2019-08-23 | - |
dc.identifier.uri | http://localhost:8080/xmlui/handle/123456789/1314 | - |
dc.description.abstract | Single-source clocking is important for networked SoC architectures. This article discusses the validation challenges related to on-chip single-source clocking due to the distributed clocking trends of recent SoCs and proposes a new low cost and no SoC re-spin solution. - Paul Bogdan, University of Southern California. © 2013 IEEE. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Implications of on-chip single-source clocking on high-speed serial interfaces in network soc | en_US |
dc.type | Article | en_US |
Appears in Collections: | Year-2019 |
Files in This Item:
File | Description | Size | Format | |
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Full text.pdf | 966.01 kB | Adobe PDF | View/Open Request a copy |
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