Ultra low energy reduced switching DAC for SAR ADC

Abstract

This paper presents a novel architecture for a lowenergy Digital-to-Analog converter (DAC) used in Successive Approximation Register Analog-to-Digital converters (SAR ADCs). The proposed ultra low-energy reduced switching (RS) architecture for DAC employs a new charge sharing and restoration technique for generating the desired voltage. Using its unique capacitor array and switching technique, it reduces the energy consumption for capacitor charging by 99.85% (for 10-bit) as compared to conventional SAR ADC. The proposed architecture requires a fewer number of switches as compared to other lowenergy architectures and efficiently reduces the switching energy as well.