Modeling and characterization of VBUS power discharge for embedded superspeed USB host/devices

Abstract

After the expiry of serial ports for desktops and laptops, serial interface came into picture and out of serial interface USB (superspeed USB) has become the most common peripheral interface. In addition, built-in (embedded) USB applications are on the rise around the world. But development teams that implement the USB interface in the embedded system can easily produce slight variations such that interoperability with other USB devices could result in uncertain results. These uncertain results generally lead to the enumeration as well as data transfer failures in the embedded system. Sometimes, enumeration failure occurs due to system power management efforts. In an embedded system, it might be desirable to have a USB host dynamically power down an attached USB device as part of its power management scheme. The problem is, the USB 2.0/3.x specification does not provide for a discharge mechanism on the host/device side for VBUS power. Till now no analytical estimation has been provided for this limitation. In this paper mathematical modeling and its characterization has been done to resolve above limitation. Electrical characterization of VBUS power discharge mechanism is explored extensively to determine discharge time. This mathematical model has been developed to help embedded system developer and designer to get exact discharge time for their system according to their devices used. Further this model and its characterized results have been verified using circuit simulation as well as at real 16nm SoC as USB 2.0/3.x host and four USB implementers Forum (USBIF) certified devices. First time this kind of analytical estimation has been provided through mathematical modeling and characterization.