Fabrication, characterization and analysis of non-volatile memory devices based on colloidal metal nanoparticles

Abstract

Conventional floating gate non-volatile memory (NVM) has been a dominating NVM device until the date. Since the concept of semiconductor nanoparticles (NPs) based NVM was first proposed, it has been widely explored as potential solution to the scaling down needs of NVM device. NPs based floating gate NVM devices have several advantages as compared to its continuous floating gate based NVM devices. Further, there is intense research going on to overtake the dominance of the floating gate flash memory device technology. Therefore, a number of emerging random access memory (RAM) which are also possess nonvolatility, being investigated. These includes RRAM, MRAM, FeRAM and PCM mainly. However, there is still a long way to cover before they can beat the flash memory dominance, which has already adopted the three-dimensional (3D) architecture to survive the scaling needs for, further next years. Therefore, the primary focus in the thesis would be on mainly the NPs based NVM devices and extending it to RRAM synaptic devices towards the end chapter. A process for NPs synthesis and deposition is identified after reviewing a number of research on NPs based NVM devices, which have used a number of different processes. In summary, it is found that previous process lack in simplicity, control over the sizes of the NPs, requiring high thermal budget, usually complex and costly in nature. In present thesis work, a colloidal synthesis and spin-coating based process is proposed and studied for NPs based NVM devices. The work start with identifying the suitable materials for NVM device applications. In particular, Ni and Co are identified as potential candidates for device experiments. A number of colloidal synthesis processes are studied in order to identify suitable methods for synthesis and size control of metal (Ni and Co) NPs up to below 10 nm and 1-2 nm for some samples. Samples are characterized by DLS, HRTEM, SEM/EDX, XRD and AFM characterization techniques. The spin coating and experimental conditions, which provide the most uniformly distributed NPs over a device substrate, are selected for the further device fabrication. AFM and SEM/EDX study is also done to confirm the NPs sizes and material presence at the NPs spin-coated device substrates. After having done the process optimizations and identification of optimized process parameters, the devices are fabricated and characterized. The MOS NVM devices which are fabricated usually have 3-4 nm thick tunnel dielectric of SiO2, typically a monolayer of spin coated NPs and 10-13 nm of control dielectric in different fabricated samples. Co-NPs of an average size of 5 nm are used for MOS NVM device fabrication and they result in very big memory window of 8V after application of sweep voltage of ±6V. The big memory window by the devices are one of the excellent finding of the work. In addition, devices are tested for actual device program/erase and retention. Device show a robust retention trend and extrapolated calculation indicated the retention more than 10 years. Ni-NPs based MOS NVM devices also show reasonably good memory window of 4V at ±10V and good retention trend. Further chapters shows Co-NPs scaling down to 1-2 nm size and being used for MOS NVM devices fabrication. These devices results in a shift in flat band voltage, ΔVFB of 0.35‒1.5V by applying 1.2‒4V sweep voltages, which evidences the low operating voltage, low power and highly scalable NVM applications. In this section, the fabrication of devices are repeated for a number of times to check reproducibility and it is found to be reasonably good reproducibility for device characteristics from device to device and from one sample to another sample. In the end section, a study on application of 1-2 nm Co-NPs for the RRAM synaptic devices is done. The primary analysis of the fabricated NPs based RRAM synaptic devices show very useful I-V characteristics. The RRAM devices demonstrate switching with dual mode interchangeable SET and RESET characteristics where it opens on SET side at higher voltage while other side it RESET at relatively low voltage. Characteristics of such a RRAM device is useful in neuromorphic applications, primarily by embedding them crossbar arrays. These devices are the capable of Hebbian spiking timing dependent plasticity (STDP) and anti-Hebbian STDP that can be used in supervised spiking neural network for neuromorphic computing applications.