Simulation-based impedance characterization of PDN in high-performance multi-chip HTCC packages for avionics

Abstract

High-Speed Multi-Chip HTCC Packages for Avionics require careful considerations early in the design cycle to obtain the optimum electrical performance. Some design goals can be achieved with simple stackup or layout modifications, but others require a detailed analysis using electromagnetic field solvers [1-3]. This paper proposes a design methodology and various guidelines to meet the optimum electrical performance in terms of Power Integrity. The methodology presented here is based on different sections of power and ground net pairs and is supported by extensive simulation results.