Efficient and Lightweight FPGA-based Hybrid PUFs with Improved Performance

Abstract

In recent years, Physically Unclonable Functions (PUFs) have emerged as a promising technique for hard- ware based security primitives because of its inherent uniqueness and low cost. In this paper, we present an area efficient hybrid PUF design on field-programmable gate array (FPGA). Our approach combines units of conventional RS Latch-based PUF (RS-LPUF) and Arbiter-based PUF (A-PUF) which is then aug- mented by the programmable delay lines (PDLs) and Temporal Majority Voting (TMV) for performance enhancement. The area of the hybrid PUF is relatively high when compared to few conventional PUF designs, but is significantly small when compared to other composite and hybrid PUF designs reported so far. The measured results on the Xilinx Spartan-6 FPGA demonstrate PUF signatures exhibits good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing.