Noise-power-area optimised design procedure for OTAs with complementary input transistors for neural amplifiers

Abstract

Simultaneous measurement of neural bio-potentials from a large number of neurons is finding applications in a diverse range of areas such as healthcare and brain-machine interfacing. Neural amplifiers used for these measurements have a tight specification of low-power, low-noise and small area. Most of the reported neural amplifiers use operational transconductance amplifier (OTA) based capacitive feedback amplifiers to meet these requirements. In this study, for the first time, a novel systematic noise-power-area optimised design procedure, for complementary input transistor based OTAs, used frequently in neural amplifiers is proposed. By applying the proposed design procedure, the authors have presented a neural amplifier design that is split into two stages to reduce area requirement and enhance linearity at the expense of slight degradation in noise efficiency factor. The presented design achieves 2.1 μVrms noise in the integration bandwidth of 0.2 Hz–8 kHz with 7.7 μA total current in a die area of 355 μm × 175 μm in 180 nm CMOS technology. The presented design procedure is inherently technology agnostic. The novelty lies not in the architecture of the proposed neural amplifier, but in the proposed design procedure to optimise the noise-power-area trade-off in CMOS amplifier circuit design.