Quality reliability assessment of USB-PLL clock failure in silicon products

Abstract

Quality and reliability are one of the crucial test features in post silicon validation which ensures the performance of flawless silicon production. This paper addresses the issue related to random clock valid failure of USB-PLL during the series of reliability testing on 28nm SoC product. However, in existence of such an unpredictable issue, silicon production cannot happen; though during the design verification and functional validation, the USB PLL clock valid was working as per design. To avoid production discontinuation, a permanent solution is need of the hour. So, this issue has been replicated on analog bench validation for further debugging and rootcausing. During the debugging, PHY’s clock validity issue was isolated and PLL clock was not obtained at digital logic of the USB. Thus, we propose the immediate solution for this productlevel reliability problem by adding a reset sequence through a software setting. In addition to above, designers have been requested for thorough review of robustness of the oscillator concept to optimize this issue from designer perspective.