Please use this identifier to cite or link to this item: http://dspace.iitrpr.ac.in:8080/xmlui/handle/123456789/2978
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dc.contributor.authorVelampati, R. S. R.-
dc.contributor.authorHasaneen, E.- S.-
dc.contributor.authorHeller, E. K.-
dc.contributor.authorJain, F. C.-
dc.date.accessioned2021-10-10T06:07:10Z-
dc.date.available2021-10-10T06:07:10Z-
dc.date.issued2021-10-10-
dc.identifier.urihttp://localhost:8080/xmlui/handle/123456789/2978-
dc.description.abstractThis paper presents nonvolatile memory characteristics of a quantum dot gate floating gate nonvolatile memory (QDNVM) that employs SiOx-cladded silicon quantum dots as discrete charge storage nodes of the floating gate. The cladding of Si quantum dots and control of their size are shown to result in a faster access and improved retention time. The floating gate is formed by site-specific self-assembly of SiOx-Si quantum dots on the tunnel oxide layer over the p-region between source and drain of an n-channel field-effect transistor (FET). Experimental data on fabricated long channel devices show threshold voltage shift as a function of duration and magnitude of the electrical stress applied during the “Write” operation. Current–voltage characteristics (ID–VD and ID–VG) are presented before and after stress. The electrical characteristics are explained using a quantum dot gate FET model which includes the threshold voltage shift (VTH) as a function of charge on the floating gate quantum dots due to applied electrical stress.en_US
dc.language.isoen_USen_US
dc.subjectFloating gate field-effect transistor (FET)en_US
dc.subjectnonvolatile memoryen_US
dc.subjectquantum doten_US
dc.subjectretention time.en_US
dc.titleFloating gate nonvolatile memory using individually cladded monodispersed quantum dotsen_US
dc.typeArticleen_US
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