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dc.contributor.authorSingh, P.-
dc.contributor.authorSingh, M. K.-
dc.contributor.authorHande, V. G.-
dc.contributor.authorSakare, M.-
dc.date.accessioned2021-11-16T18:29:22Z-
dc.date.available2021-11-16T18:29:22Z-
dc.date.issued2021-11-16-
dc.identifier.urihttp://localhost:8080/xmlui/handle/123456789/3190-
dc.description.abstractThis paper presents an inductor less D-latch for high-speed integrated circuits. The proposed D-latch uses negative feedback, which makes the high-frequency input impedance appear inductive. This effect increases the bandwidth by about 23%. The proposed latch operation is verified using two highspeed integrated circuit applications, i.e., A pseudo-random binary sequence (PRBS) generator and a serializer. The PRBS generator and the serializer show an improvement of 15.8% and 23%, respectively, using the proposed latch. Results are confirmed using post-layout simulation in standard 90 nm CMOS technology with 1 V supply.en_US
dc.language.isoen_USen_US
dc.subjectD-Latchen_US
dc.subjectPRBSen_US
dc.subjectDigital circuitsen_US
dc.subjectlow poweren_US
dc.subjectCML logic.en_US
dc.titleDesign of a PRBS generator and a serializer using active inductor employed CML latchen_US
dc.typeArticleen_US
Appears in Collections:Year-2021

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