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DC Field | Value | Language |
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dc.contributor.author | Pathania, S. | - |
dc.contributor.author | Gupta, P. | - |
dc.contributor.author | Kumar, R. | - |
dc.contributor.author | Kumar, S. | - |
dc.date.accessioned | 2022-08-25T16:25:45Z | - |
dc.date.available | 2022-08-25T16:25:45Z | - |
dc.date.issued | 2022-08-25 | - |
dc.identifier.uri | http://localhost:8080/xmlui/handle/123456789/3911 | - |
dc.description.abstract | It has reached a period when the search beyond silicon for utilizing it in a transistor has increased genuine significance. Graphene is described as a crystalline allotrope of carbon with two-dimensional properties arranged in the hexagonal lattice form. It's one of the uses in designing field-effect transistors (FET) such as graphene field-effect transistors. It is explored for the future of flexible electronics devices applications due to the promising graphene attributes. There is some parameter that decides the performance such as speed, uniformity, and reliability of the GFET. One can use graphene field-effect transistors (GFET) to design analog and digital applications for future technology nodes. In this paper, we present a mathematical model of flexible bilayer dual-gated graphene FETs and implement it in a Verilog-A. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Bending effect | en_US |
dc.subject | Bilayer | en_US |
dc.subject | Dual-gate | en_US |
dc.subject | Flexible electronics | en_US |
dc.subject | Graphene field-effect transistor | en_US |
dc.subject | Modeling | en_US |
dc.subject | Verilog-A | en_US |
dc.title | Design and performance benchmarking of dual gate flexible bilayer graphene FETs | en_US |
dc.type | Article | en_US |
Appears in Collections: | Year-2021 |
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