Emerging Interconnect Technologies for 3D Networks-on-Chip

Abstract

Historically, microchip design has some or all of these functional blocks: computational, storage, communication, and I/O. Microchip technologies have evolved from large-scale integrated (LSI) to very-large-scale integrated (VLSI) to ultra-large-scale integrated (ULSI) systems. The current ULSI technology, where the chip itself constitutes the entire functional system, defines a modern system-on-chip [1]. As per the International Technology Roadmap for Semiconductors (ITRS) projections, with every next-generation technology node, interconnect effects dominate performance. In that, relative delay in global wires could be manyfold longer than that of local wires or logic gates [2]. Process variations, cross talk, and electromagnetic interference (EMI) can further degrade the performance of these global interconnects. With technology scaling and faster speeds, global synchronization is becoming a mirage. Designers are often required to adopt alternative timing mechanisms including designing globally asynchronous locally synchronous (GALS) chips. While the last decade has seen significantly reduced design cycles, complexity has scaled up several times over the same period of time. Thus, we need a modular approach to design hardware and software, which allows reuse of IPs, so that the key performance metrics, such as reliability, scalability, energy bounds, and manufacturing costs, are met.