Signal integrity analysis of high speed onchip and chip-to-chip copper interconnects

Abstract

The aggressive scaling of on-chip interconnects leads to a significant increase in coupling capacitance. This causes crosstalk effects, especially for technology nodes at the end of the roadmap. In addition, surface roughness is viewed as the major contributing factor to conductor losses, which further aggravates crosstalk-induced effects. An analysis is provided of crosstalkinduced effects considering the surface roughness of the interconnect at current and future technology nodes (13nm, 7nm) for on-chip global Copper interconnects. To perform our analysis, we used an Aggressor Victim Aggressor 3-line bus architecture and FINFET-based driver circuits based on binary input logic. In our work, we also discuss the relevance of repeater insertion in rough interconnects. In designing high-performance on-chip interconnects, repeaters are one way to minimize power losses and propagation delays. Repeaters are buffers or inverters made of complementary metal oxide semiconductor (CMOS) or other advanced transistors. Our work comprises the development of an artificial neural network (ANN) framework for quantifying the statistics of the optimal number and size of repeaters that are needed to minimize the power delay product of rough copper on-chip interconnects. The proposed ANN framework enables the use of analytic mathematical expressions instead of expensive and repeated SPICE simulations and evaluations of a particle swarm optimization (PSO) algorithm to solve the repeater optimization problem. Due to this ANN framework, Monte Carlo-based statistical analysis of the optimal number and size of repeaters can be conducted extremely quickly with this ANN framework. With an increase in signal speeds, small imperfections begin to affect the performance of interconnects. It is a fact that thermal effects are integral aspects of interconnects, such as selfheating caused by current flow, as well as environmental heating in high-speed designs. Due to high computational power and increased component density, printed circuit boards (PCBs) have a greater thermal budget. A major role is played by thermal effects in the performance of high-speed interconnects. It is extremely important to design high-speed interconnects that are reliable and efficient at the board level. We present thermal effects on the insertion loss, crosstalk, and phase of high-speed signals. Additionally, this study examines the thermal sensitivity of various aspects of interconnect design, such as interpair spacing, trace height, and dielectric thickness. We also examine the thermal sensitivity for standard loss, mid-loss, lowloss, as well as ultra-low loss dielectric materials. Moreover, this study also examines the major heat sources contributing to thermal effects in high-speed PCB interconnections. Two different high-speed interconnect topologies are considered in our analysis. An electrothermal methodology (EEM) is presented for the design of high-speed PCB interconnects for reliable and efficient system design. An electrical-thermal co-simulation is performed using our proposed EEM. In addition, we provide an artificial neural network (ANN)-based model for reliable and efficient interconnect design which is faster and requires significantly fewer computations. Our analysis shows that the proposed ANN model is five orders of magnitude faster than the EEM. Based on our reported EEM, we are able to develop reliable and efficient methods of designing high-speed interconnect topologies that offer space and cost savings, as well as ensuring the system's accuracy. It could be used for designing high-performance servers, storage systems, and network cards.