Please use this identifier to cite or link to this item: http://dspace.iitrpr.ac.in:8080/xmlui/handle/123456789/4363
Title: 6-bit 1-GS/s Partially Active Flash ADC with Comparator Offset Correction
Authors: Sharma, N
Hande, v.
Srivastava, R.K.
Das, D.M.
Keywords: Flash analog-to-digital converter (ADC)
offset correction
low-power
partially active comparator.
Issue Date: 26-Mar-2023
Abstract: This paper presents a low-power 6-bit 1 GS/s partially active flash analog-to-digital converters (ADC) in 65-nm CMOS technology. A novel comparator offset correction technique is proposed, which does not require additional foreground calibration cycles. The partially active second-stage comparison is employed for power efficiency. A third-stage comparison is introduced for offset correction using fifteen low-offset comparators, out of which two are activated. The 0.5-bit redundancy from the first-stage provides the tolerance to track-and-hold (T/H) buffer settling error for high-speed applications. The simulation results show that the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 36.36 dB and a spurious-free dynamic range (SFDR) of 48.65 dB at a Nyquist frequency of 500 MHz with the power consumption of 13.98 mW.
URI: http://localhost:8080/xmlui/handle/123456789/4363
Appears in Collections:Year-2022

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