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dc.contributor.authorBadri, S.-
dc.contributor.authorSaini, M.-
dc.contributor.authorGoel, N.-
dc.date.accessioned2024-10-13T17:13:59Z-
dc.date.available2024-10-13T17:13:59Z-
dc.date.issued2024-10-13-
dc.identifier.urihttp://dspace.iitrpr.ac.in:8080/xmlui/handle/123456789/4732-
dc.description.abstractBatteryless technology evolved to replace battery technology. Nonvolatile memory (NVM)-based processors were explored to store the program state during a power failure. The energy stored in a capacitor is used for a backup during a power failure. Since the size of a capacitor is fixed and limited, the available energy in a capacitor is also limited and fixed. Thus, the capacitor energy is insufficient to store the entire program state during frequent power failures. This article proposes an architecture that assures safe backup of volatile contents during a power failure under energy constraints. Using a proposed dirty block table (DBT) and writeback queue (WBQ), this work limits the number of dirty blocks in the L1 cache at any given time. We further conducted a set of experiments by varying the parameter sizes to help the user make appropriate design decisions concerning their energy requirements. The proposed architecture decreases energy consumption by 17.56%, the number of writes to NVM by 18.97% at last level cache (LLC), and 10.66% at a main-memory level compared to baseline architecture.en_US
dc.language.isoen_USen_US
dc.subjectIntermittent poweren_US
dc.subjectlimited energyen_US
dc.subjectnonvolatile memory (NVM)en_US
dc.subjectphase change memory (PCM)en_US
dc.subjectspin-transfer torque RAM (STT-RAM)en_US
dc.titleAn Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraintsen_US
dc.typeArticleen_US
Appears in Collections:Year-2023

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