Design of Non-Volatile Processors for Intermittent Computing

Abstract

Internet of Things (IoT) devices are rapidly expanding in many areas, including deep mines, space, industrial environments, and health monitoring systems. Most sensors and actuators are battery-powered, and these batteries have a finite lifespan. Maintenance and replacement of these many batteries will increase the maintenance cost of IoT systems and cause massive environmental damage. Energy Harvesting Devices (EHDs) are an alternative and promising solution to these battery-operated IoT devices. The energy harvester stores enough energy in a capacitor to power the embedded device and compute the task. This type of computation is known as intermittent computing. Energy harvesters cannot provide continuous power to embedded devices, resulting in power failures in the IoT system. On conventional processors, all registers and caches are volatile. We require a processor that consists of Non-Volatile Memory (NVM) at either the cache or main memory level to store volatile contents during a power failure. We must use NVM at either the cache or main memory levels to design an NVM-based processor. NVM caches degrade system performance and use more energy than volatile caches. Using a pure NVM at L1 reduces system performance by 45.93%, inspiring the idea of an efficient hybrid cache architecture. We propose efficient placement and migration policies for a hybrid cache architecture at L1 that uses volatile memory and NVM. The proposed architecture includes cache block placement and migration policies to reduce the number of writes to NVM. During a power failure, the backup strategy identifies and migrates critical blocks from the volatile memory region to NVM. The energy stored in a capacitor is used as a backup during a power failure. Because the size of a capacitor is fixed and limited, the available energy in a capacitor is also limited and f ixed. Thus, the capacitor energy cannot store the entire program state during frequent power failures. We propose an NVM-based architecture at the last-level cache (LLC) that ensures safe backup of volatile contents during a power failure under energy constraints. Using a proposed dirty block table (DBT) and a writeback queue (WBQ), the proposed architecture limits the number of dirty blocks in the L1 cache at any given time. We conducted experiments by varying the parameter sizes to help users make appropriate design decisions regarding their energy requirements. Recent NVM-based microcontrollers, such as MSP430FR6989 and MSP430F5529, comprise hybrid main memory. Such devices have small volatile memory and large non-volatile memory. To make the system energy efficient, we need to use volatile memory efficiently. Therefore, we must select some portions of the application and map them to volatile memory or NVM. We propose an Integer Linear Programming (ILP) based memory mapping technique for intermittently powered IoT devices. Our proposed technique gives an optimal mapping choice that reduces the system’s Energy-Delay Product (EDP). We validated our system using TI-based MSP430FR6989 and MSP430F5529 development boards.