Please use this identifier to cite or link to this item: http://dspace.iitrpr.ac.in:8080/xmlui/handle/123456789/492
Full metadata record
DC FieldValueLanguage
dc.contributor.authorPendyala, P.-
dc.contributor.authorPasupureddi, V.S.R.-
dc.date.accessioned2016-11-19T09:01:25Z-
dc.date.available2016-11-19T09:01:25Z-
dc.date.issued2016-11-19-
dc.identifier.urihttp://localhost:8080/xmlui/handle/123456789/492-
dc.description.abstractThis work proposes a MIL-STD-1553B remote terminal controller: RT-MIL-STD-1553+, which processes data rates of 100-Mb/s over 1553 buses. This redesigned controller has three major architectural enhancements over the current 1-Mb/s controllers. Firstly, it incorporates a synchronous back-end and host processor interface to a true dual port memory to enable faster memory accesses. Secondly, the controller employs a majority-based sampling free-running decoder, suitable to interface with 100-Mb/s analog transceivers. Thirdly, the remote terminal protocol control unit has scaled-up state machines to manage the scheduling, storage and retrieval of 1553 messages, to ensure this increased throughput. The proposed remote terminal controller has been implemented in 1.2 V, 65-nm CMOS technology. Performance results show a power consumption of 14.59 mW at 100-Mb/s data rate for a 100 percent duty cycle, occupying an area of 104981 μm2, for a target BER of 10-7.en_US
dc.language.isoen_USen_US
dc.subjectArchitectural enhancementen_US
dc.subjectCMOS technologyen_US
dc.subjectProcessor interfacesen_US
dc.subjectProtocol controlen_US
dc.subjectRemote terminalsen_US
dc.titleRT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data rateen_US
dc.typeArticleen_US
Appears in Collections:Year-2015

Files in This Item:
File Description SizeFormat 
Full Text.pdf658.8 kBAdobe PDFView/Open    Request a copy


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.