Exploration of gate-all-around MOSFETs for digital, RF, and neuromorphic applications

Abstract

The dimensional and functional scaling of MOSFET dimensions has been a key enabler of advancements in the semiconductor industry, enhancing both performance and integration density. As MOSFET scaling approaches its fundamental physical limits, new material and architecture are being explored to sustain progress. Gate-all-around (GAA) devices, particularly nanowire (NW) and nanosheet (NS) FETs, have demonstrated exceptional switching performance, which positions them as strong candidates for ultra-scaled CMOS technology. Additionally, the charge-trapping mechanism in these devices offers a compelling opportunity to develop brain-inspired neuromorphic computing systems, which address the energy and speed constraints inherent in traditional von Neumann computer architecture. As experimental advancements in GAA devices accelerate, several key questions emerge regarding their integration into advanced circuits: (i) What is the most promising GAA architecture for digital and radio frequency (RF) applications? (ii) Which CMOS inverter stacking configuration with NS-FET provides the most significant performance improvements with high integration density at ultra-scaled gate lengths? (iii) How can the charge-trap mechanism in NW-FETs be better utilized to achieve multiple stable states for emulating biological synapses? (iv) Is it possible to develop energy-efficient and highly scalable spiking neural networks with NW-FET by exploiting the charge-trap mechanism? The thesis work is focused on answering the above questions by performing device-to-circuit level co-optimization of GAA devices using a well-calibrated 3D TCAD tool, based on self-consistent solutions of the Boltzmann’s transport equation and Poisson’s equation with incorporating quantum corrections and mobility degradation effects. Initially, GAA devices, including NW-FET and NS-FET, are investigated for analog/RF applications and benchmarked against their Fin-FET counterparts. The findings indicate that NS-FET is well-suited for analog/RF applications due to their high voltage gain, superior cut-off frequency, and maximum oscillation frequency for sub-5 nm technology nodes. Subsequently, innovative CMOS inverter configurations, such as forksheet (FSH) and complementary FET (CFET), are explored in conjunction with nanosheet to develop high-speed and low-power digital ICs with high integration density. This analysis demonstrates that CFET delivers optimal and robust switching performance in the inverter, SRAM, and ALU configurations at the ultimate scaling limit. In the next phase, a systematic analysis was conducted to assess the viability of NW channel as charge-trap transistor (CTT) for emulating synapses at the 5 nm technology node. This study focuses on understanding the role of device parameters on short-term and long-term memory. Importantly, the nearly linear conductance modulation of NW-CTT as a synapse promises high recognition accuracy of around 94.7% and low write energy (2.3 mJ) in a neural network configuration (784 × 100 × 10) for handwritten digit recognition. Finally, the successful co-integration of neurons and synapses using NW-CTT is demonstrated for scalable neuromorphic hardware with CMOS-compatible processing techniques. The neurons and synapses are co-integrated to develop a spiking neural network, which exhibits noise-tolerant and energy-efficient recognition for handwritten digits. The comprehensive analysis suggests that NW-CTT presents a promising solution for high-density and low-power hardware implementations of brain-inspired spiking learning systems.