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DC Field | Value | Language |
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dc.contributor.author | Kumar, V. | - |
dc.contributor.author | Sharma, R. | - |
dc.contributor.author | Uzunlar, E. | - |
dc.contributor.author | Zheng, L. | - |
dc.contributor.author | Bashirullah, R. | - |
dc.contributor.author | Kohl, P. | - |
dc.contributor.author | Bakir, M.S. | - |
dc.contributor.author | Naeemi, A. | - |
dc.date.accessioned | 2016-11-24T06:27:57Z | - |
dc.date.available | 2016-11-24T06:27:57Z | - |
dc.date.issued | 2016-11-24 | - |
dc.identifier.uri | http://localhost:8080/xmlui/handle/123456789/609 | - |
dc.description.abstract | Frequency and time domain models are developed for backplane (BP), printed circuit board (PCB), and silicon interposer (SI) links using six-port transfer matrices (ABCD matrices) for bumps, vias and connectors, and coupled multiconductor transmission lines for traces. The six-port transfer matrix approach enables easy computation of the transfer function, as well as near-end and far-end crosstalk. The intersymbol interference is accounted for by computing the pulse response for the worst case bit pattern. Furthermore, the models developed here are used to optimize the data-rate and trace width for each of the links, so that the aggregate bandwidth obtained per joule of energy supplied to the link is maximized. The modeling and optimization approach developed here serves as a good platform to compare the air-gap interconnects against BP, PCB, and SI interconnects on lossy dielectrics. It is shown that air-gap interconnects can provide an aggregate bandwidth improvement of (3× )-(4× ) for BP links at a comparable energy per bit, and a (5× )-(9× ) improvement in aggregate bandwidth of PCB links at the expense of 20% higher energy per bit. For SI links, air-gap interconnects are shown to provide a (2× )-(3× ) improvement in aggregate bandwidth and a (1× )-(1.5× ) improvement in energy per bit. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Air-gap interconnects | en_US |
dc.subject | Chip-to-chip interconnects | en_US |
dc.subject | Data-rate and trace-width co-optimization | en_US |
dc.subject | Fine-pitch interconnects | en_US |
dc.subject | Silicon interposer (SI) | en_US |
dc.subject | Time-domain modeling | en_US |
dc.title | Airgap interconnects: Modeling, optimization, and benchmarking for backplane, PCB, and interposer applications | en_US |
dc.type | Article | en_US |
Appears in Collections: | Year-2014 |
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File | Description | Size | Format | |
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Full Text.pdf | 4.07 MB | Adobe PDF | View/Open Request a copy |
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