Modeling, fabrication and performance benchmarking of on-chip and chip-to-chip interconnects considering surface roughness

Abstract

As the dimensions of the interconnects scale down, the losses and electromigration occurred in Cu interconnects become a serious concern. The conductor losses further increase at higher frequency due to skin effect phenomenon. One of the main contributor to the conductor losses at lower technology nodes and high frequency is the surface roughness, which is due to process limitation or intentionally introduced to increase the adhesion between metal and dielectric. In on-chip Cu interconnects, as the technology scales down, size effects comes into picture as thickness becomes comparable or less than the bulk mean free path. These size effects further aggravate and lead to increased penalty on the Cu interconnect performance when we consider the surface roughness in Cu lines. This thesis aims towards developing compact models to find the effect of realistic surface roughness on the RLC parameters of on-chip and chip-to-chip Cu interconnects. The realistic surface roughness profile parameters are extracted by fabricating and performing AFM analysis of the interconnect test structures. We also benchmark the performance of rough surface on-chip & chip-to-chip Cu interconnects against smooth interconnects. Closed-form analytical models to find the surface roughness effect on resistivity and mean free path of on-chip interconnects at various current and future technology nodes are also proposed. It is seen that surface roughness is utmost important for accurate parameter extraction of on-chip and chip-to-chip Cu interconnects. In that context, the following contributions are made in this thesis: First, we model the closed form expressions for resistivity and mean free path of onchip Cu interconnects at 45nm, 22nm, 13nm, and 7nm technology nodes. The closed form expressions are obtained from a generalized surface and grain boundary scattering approach that is combined with Mandelbrot-Weierstrass (MW) fractal function. For local/intermediate and global interconnects at 13nm technology node, effective resistivity increases by 2.5X and 2.4X, respectively, as compared to smooth lines. Similarly, the MFP due to rough surfaces decreases by 29% for local/intermediate and by 26% for global interconnects. Next, we present analytical models for RLC p.u.l. extraction for these technology nodes by using the extracted roughness parameters from the AFM analysis of fabricated thin sheets. We also present signal integrity analysis using the eye diagram at 1Gbps, 5Gbps, 10Gbps and 18Gbps bit rates and computational overhead incurred during simulation for different values of roughness and technology nodes. For 1Gbps data rate, the vertical and horizontal eye openings reduce by 27% and 62%, respectively, when compared to smooth line. Our results show that as the data rates increase, the eye opening decreases and peak to peak jitter increases. We also present analytical model to extract RLC p.u.l. and performance evaluation of chip-to-chip copper interconnects at several gigahertz frequency range considering experimentally measured fractal surface roughness. It is seen that, propagation delay increases by 2.6X while EDP goes up by 2.8X for backplane (BP) rough interconnects when compared against smooth lines at 50cm interconnect length and 100GHz. Similarly, penalty on bandwidth density (BWD) due to roughness is 61% for BP links. Finally, by using our proposed models, we present the effect of considering rough interconnections in mesh topology based NoCs. Based on the above studies, it is concluded that surface roughness is one of the most important factors for delay and losses in on-chip and chip-to-chip Cu interconnects. Developing process to mitigate interconnect surface roughness is therefore the need of the hour.