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Results 1-10 of 16 (Search time: 0.003 seconds).
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Issue DateTitleAuthor(s)
24-Aug-2019Modeling and characterization of VBUS power discharge for embedded superspeed USB host/devicesPandey, M.K.; Goyal, M.; Sharma, P.K.; Sharma, R.
5-Dec-2019Analyzing crosstalk-induced effects in rough on-chip copper interconnectsPathania, S.; Kumar, S.; Sharma, R.
29-Nov-2019Threshold effect of bank-specific determinants of non-performing assets: an application in Indian bankingBardhan, S.; Sharma, R.; Mukherjee, V.
11-Dec-2019Foreword: special section on packaging and interconnects: cutting-edge solutions in modeling, design, and characterization—part ITelescu, M.; Gu, X.; Sharma, R.
23-Aug-2019Implications of on-chip single-source clocking on high-speed serial interfaces in network socPandey, M.K.; Gupta, T.; Sharma, R.
11-Dec-2019Foreword: special section on packaging and Interconnects: cutting-edge solutions in modeling, design, and characterization—Part IITelescu, M.; Gu, X.; Sharma, R.
12-Aug-2021Multiphysics approach using computational fluid dynamics for signal integrity analysis in high speed serial linksPathania, S.; Vasa, M.; Shrivastava, A.; Kumar, S.; Kumar, V.; Muthusamy, S.; Seema, P.K.; Mutnury, B.; Sharma, R.
12-Aug-2021Dual current based power discharge model for embedded USB Host-Devices systemPandey, M. K.; Goyal, M.; Sharma, P. K.; Sharma, R.
12-Aug-2021Temperature-Aware Closed-Form matrix rational approximation model for crosstalk analysis of Multi-Walled carbon nanotube interconnectsGuglani, S.; Kumar, A.; Kumar, R.; Kaushik, B. K.; Sharma, R.; Achar, R.; Roy, S.
13-Aug-2021Quality reliability assessment of USB-PLL clock failure in silicon productsPandey, M. K.; Sinha, A. K.; Sharma, P. K.; Sharma, R.

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