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Results 11-20 of 24 (Search time: 0.003 seconds).
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Issue DateTitleAuthor(s)
20-Jun-2021Estimating per-unit-length resistance parameter in emerging Copper-Graphene hybrid interconnects via prior knowledge based accelerated neural networksKumar, R.; Narayan, S. S. L.; Kumar, S.; Roy, S.; Kaushik, B. K.; Achar, R.; Sharma, R.
24-Jun-2021Role of grain Size on the effective resistivity of Cu-Graphene hybrid interconnectsKumar, R.; Pathania, S.; Guglani, S.; Kumar, A.; Kumar, S.; Roy, S.; Kaushik, B. K.; Sharma, R.
29-Jun-2021Temperature-Aware compact modeling for resistivity in Ultra-Scaled Cu-Graphene hybrid interconnectsKumar, R.; Kumar, S.; Guglani, S.; Roy, S.; Kaushik, B. K.; Sharma, R.; Achar, R.
12-Aug-2021Multiphysics approach using computational fluid dynamics for signal integrity analysis in high speed serial linksPathania, S.; Vasa, M.; Shrivastava, A.; Kumar, S.; Kumar, V.; Muthusamy, S.; Seema, P.K.; Mutnury, B.; Sharma, R.
19-Aug-2021Bilayer graphene/HgCdTe based self-powered mid-wave IR nBn photodetectorBansal, S.; Prakash, K.; Sharma, R.; Jain, P.; Gupta, N.; Singh, A. K.; Sardana, N.; Kumar, S.
1-Sep-2021Investigating the role of interconnect surface roughness towards the design of poweraware network on chipKumar, S.; Sharma, R.
20-Sep-2021Analytical model for inverter design using floating gate graphene field effect transistors (Nishad, A. K.; Dalakoti, A.; Jindal, A.; Kumar, R.; Kumar, S.; Sharma, R.
27-Sep-2021Design space exploration of through silicon vias for high-speed, low loss vertical linksKumar, S.; Kaur, S.; Bakshi, M.; Bansal, M.; Choudhary, M.; Sharma, R.
4-Oct-2021A high-k, metal gate vertical-slit FET for ultra-low power and high-speed applicationsKumar, S.; Kaur, S.; Sharma, R.
10-Oct-2021Performance modeling and broadband characterization of chip-to-chip interconnects with rough surfacesKumar, S.; Sharma, R.

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