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Issue Date	Title	Author(s)
23-Nov-2016	Analytical model for inverter design using floating gate graphene field effect transistors	Nishad, A.K.; Dalakoti, A.; Jindal, A.; Kumar, R.; Kumar, S.; Sharma, R.
21-Nov-2016	Design space exploration of nanoscale interconnects with rough surfaces	Kumar, S.; Sharma, R.
29-Dec-2018	Analytical modeling and performance benchmarking of on-chip interconnects with rough surfaces	Kumar, S.; Sharma, R.
1-Jan-2019	Chip-to-chip copper interconnects with rough surfaces: analytical models for parameter extraction and performance evaluation	Kumar, S.; Sharma, R.
16-May-2019	Analytical model for resistivity and mean free path in on-chip interconnects with rough surfaces	Kumar, S.; Sharma, R.
5-Dec-2019	Analyzing crosstalk-induced effects in rough on-chip copper interconnects	Pathania, S.; Kumar, S.; Sharma, R.
13-Nov-2018	Investigating the role of sidewall surface roughness on the performance of through silicon vias	Kumar, S.; Pathania, S.; Sharma, R.
19-Mar-2020	Crosstalk analysis for rough copper interconnects considering ternary logic	Pathania, S.; Kumar, S.; Sharma, R.
18-Jun-2021	Temperature and dielectric surface roughness dependent performance analysis of cu-graphene hybrid interconnects	Kumar, R.; Kumari, B.; Kumar, S.; Sahoo, M.; Sharma, R.
20-Jun-2021	A temperature and dielectric roughness-aware matrix rational approximation model for the reliability assessment of Copper– Graphene hybrid On-Chip interconnects	Kumar, R.; Kumar, A.; Guglani, S.; Kumar, S.; Roy, S.; Kaushik, B. K.; Sharma, R.; Achar, R.