Abstract:
In this article, we present a high-performance hardware architecture for Elliptic curve based (authenticated)
key agreement protocol “Elliptic Curve Menezes, Qu and Vanstone” (ECMQV) over Binary Edwards Curve
(BEC). We begin by analyzing inversion module on a 251-bit binary field. Subsequently, we present Field
Programmable Gate Array (FPGA) implementations of the unified formula for computing elliptic curve point
addition on BEC in affine and projective coordinates and investigate the relative performance of these two
coordinates. Then, we implement the w-coordinate based differential addition formulae suitable for usage in
Montgomery ladder. Next, we present a novel hardware architecture of BEC point multiplication using mixed
w-coordinates of the Montgomery laddering algorithm and analyze it in terms of resistance to Simple Power
Analysis (SPA) attack. In order to improve the performance, the architecture utilizes registers efficiently and
uses efficient scheduling mechanisms for the BEC arithmetic implementations. Our implementation results
show that the proposed architecture is resistant against SPA attack and yields a better performance when
compared to the existing state-of-the-art BEC designs for computing point multiplication (PM). Finally, we
present an FPGA design of ECMQV key agreement protocol using BEC defined over GF(2251). The execution
of ECMQV protocol takes 66.47μs using 32,479 slices on Virtex-4 FPGA and 52.34μs using 15,988 slices on
Virtex-5 FPGA. To the best of our knowledge, this is the first FPGA design of the ECMQV protocol using BEC.
