Abstract:
Parallel Prefix adders are arguably the most
commonly used arithmetic units. They have been extensively
investigated at architecture level, register transfer level (RTL),
gate level, circuit level as well as layout level giving rise
to a plethora of mathematical formulations, topologies and
implementations. This paper contributes significantly to the
understanding of these parallel prefix adders in a couple of
ways. Firstly, it attempts to describe various such parallel prefix
adders in elegant and consistent formulations. Secondly, a new
family of parallel prefix adders is proposed at architecture
level. The estimates of the area-throughput characteristics for
an instance of this family are also presented. While the speeds
achieved by this instance match those achieved by the state
of the art adders, their area characteristics exhibit upto 26%
improvement.
