INSTITUTIONAL DIGITAL REPOSITORY

Browsing Year-2021 by Author "Das, S."

Browsing Year-2021 by Author "Das, S."

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  • A CMOS based high resolution All-Digital temperature sensor with low power supply sensitivity 
    Das, S.; Wadhwa, S.; Das, D. M. (2021-11-16)
    This paper presents the design of an All-DigitalTemperature Sensor (ADTS) with low power supply sensitivity (PSS). In this architecture, the delay cell-based ring-oscillator acts like a temperature sensor. The delay cells ...
  • Efficient cache resizing policy for DRAM-based LLCs in chipMultiprocessors 
    Agarwalla, B.; Das, S.; Sahu, N. (2021-07-25)
    In today’s ChipMultiprocessors (CMPs), multiple cores share the common Last Level Cache (LLC), divided into multiple banks. As the data requirement is increasing the demand for larger LLC sizes is also increasing. ...
  • Efficient on-chip communication for neuromorphic systems 
    Kumar, S.; Das, S.; Jamadar, M.M.; Kaur, J. (2022-08-26)
    Neuromorphic computing is a trending area in computer architecture which deals with the simulation of the brain on hardware. Machine learning problems are very complex to solve by simple computers that work based on ...
  • Exploiting secrets by leveraging dynamic cache partitioning of last level cache 
    Agarwal, A.; Kaur, J.; Das, S. (2021-11-29)
    Dynamic cache partitioning for shared Last Level Caches (LLC) is deployed in most modern multicore systems to achieve process isolation and fairness among the applications and avoid security threats. Since LLC has ...
  • A fairness conscious cache replacement policy for last level cache 
    Dutta, K. K.; Tanksale, P. N.; Das, S. (2021-11-29)
    Multicore systems with shared Last Level Cache (LLC) possess a bigger challenge in allocating the LLC space among multiple applications running in the system. Since all applications use the shared LLC, interference ...
  • MAPCP: Memory access pattern classifying prefetcher 
    Jamadar, M.M.; Kaur, J.; Das, S. (2022-08-22)
    Prefetching is a technique used to improve system performance by bringing data or instructions in the cache before it is demanded by the core. Several prefetching techniques have been proposed, in both hardware and software, ...
  • Towards enhanced system efficiency while mitigating row hammer 
    Goswami, K.; Banerjee, D. S.; Das, S. (2021-10-25)
    In recent years, DRAM-based main memories have become susceptible to the Row Hammer (RH) problem, which causes bits to flip in a row without accessing them directly. Frequent activation of a row, called an aggressor row, ...
  • Towards row sensitive DRAM refresh through retention awareness 
    Goel, T.; Maura, D.; Goswami, K.; Das, S.; ba, D. S. (2021-07-21)
    Dynamic Random Access Memory (DRAM) is the de-facto choice for main memories in modern day computing systems. It is based on capacitor technology, which is volatile in nature. Hence, these memories require periodic ...
  • Vapour transport grown photosensitive GeO2 thin film 
    Chowdhury, A.; Dalal, A.; Dhar Dwivedi, S. M. M.; Ghosh, A.; Halder, N.; Das, S.; Mondal, A. (2021-07-17)
    GeO2 thin film (TF) was fabricated by vapour deposition technique in a two zone horizontal quartz tube. Field emission-scanning electron microscopy showed the formation of 200 nm TF on the Si (100) substrate. The ...

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