Abstract:
Spin-transfer torque magneto-resistive randomaccess memory (STT-MRAM) is an exciting new emerging
technology, being considered as a strong candidate to fill the gaps
in the existing memory hierarchy between DRAM and the secondary memory. STT-MRAM has adequate endurance. However,
unresolved write switching and read reliability issues still exist at
the functional operating temperature corners. One biggest challenge is that the read bit error rate (RBER) is not at an acceptable
level for system reliability across the wide operating temperature range. We present an STT-MRAM memory subsystem that
is fully compatible with existing DDR-based DIMM designs and
evaluate read disturb and read sense bit-error rate (BER) under
various operating temperature conditions. We propose temperature aware adaptive techniques for reliable reads at the rank
level. The proposed temperature adaptation technique improves
overall reliability of the DDR4 STT-MRAM-based memory subsystem with an optimal read current considering an acceptable
64-byte cacheline BER. Our full system simulations show 1000×
order of improvements toward a cell raw read disturb BER along
with 5% reduction in memory power and less than 1% impact
on overall system performance.
