Abstract:
The hot carrier (HC) induced degradation has
become a major concern in advanced CMOS technologies because
of non-scalable VDD. In this work, we have shown that the HC
induced degradation in gate-first HKMG nMOS transistors can
be modulated by optimizing the device width, lanthanum capping
layer thickness, and pre-gate carbon (C) implant. The physics
responsible for these observations are investigated and attributed
to the reduction in the number of defects (traps) in hafnium oxide
(HfO2) and reduction in carrier injection into these defects. It is
also shown that the HC performance of these transistors could
be further improved by increasing the active-to-active spacing.
