Abstract:
At sub-22nm technology nodes, size effects play a
prominent role in the performance degradation of Cu
interconnects. Several scattering mechanisms contribute to size
effects, including surface roughness and grain boundary
scattering as grain sizes in Cu decreases with reduced line
widths. Due to these scattering phenomena, the resistivity of Cu
interconnects increases drastically, which leads to electrical and
thermal performance degradation and reliability issues. To
address these limitations, researchers have proposed CuGraphene hybrid interconnects, where the line resistance due to
Cu and Graphene is connected in parallel leading to smaller
effective resistances. In this paper, we present analytical models
of the reduction in effective resistivity obtained due to
enlargement of grain size. The reduction in effective resistivity
is due to the hybrid interconnect geometry and grain size
enlargement. We present a qualitative analysis for the
resistivity, mean free path, delay and energy delay product of
the three interconnect technology nodes from 22nm to 7nm Cu
widths. Our analysis shows that Cu on-chip interconnects with
Graphene as a barrier layers shows 47%, 30% and 19%
improvement in resistivity, delay and energy delay product
respectively due to grain size enlargement at 13nm technology
node.
