Abstract:
Due to highly-scaled feature sizes of on-chip
interconnects at advanced technology nodes, size effects
dominate the conductor losses. Also, the surface roughness
effectsin Cu interconnects increase due to scaling. Graphene has
been recently proposed as a barrier layer in Cu interconnects to
mitigate these conductor losses. This paper reports a
temperature-dependent compact model for resistivity and
resistance of hybrid interconnects, where each conductor
consists of a Cu interconnects with a Graphene barrier layer on
all sides. For the 7 nm technology node, our analysis shows that
hybrid interconnects has 25%, 91%, and 36% lesser resistivity
as compared to smooth, rough, and GNR interconnects,
respectively. We also present signal integrity analysis for
performance benchmarking of hybrid interconnects against
conventional Cu interconnects. For 200 Mbps data rate, eye
height and eye width for hybrid interconnects improve by 47%
and 8x as compared to that in smooth Cu interconnects.
