Abstract:
True random number generators (TRNGs) play a
fundamental role in cryptographic systems. This brief presents a
new and efficient method to generate true random numbers on
field programmable gate array (FPGA) by utilizing the random
jitter of free-running oscillators as a source of randomness. The
free-running oscillator rings incorporate programmable delay
lines (PDLs) to generate large variation of the oscillations and
to introduce jitter in the generated ring oscillators clocks. The
main advantage of the proposed TRNG utilizing PDLs is to
reduce correlation between several equal length oscillator rings,
and thus improve the randomness qualities. In addition, a Von
Neumann corrector as post-processor is employed to remove any
bias in the output bit sequence. The validation of the proposed
approach is demonstrated on Xilinx Spartan-3A FPGAs. The
proposed TRNG occupies 528 slices, achieves 6 Mb/s throughput with 0.999 per bit entropy rate, and passes all the national
institute of standards and technology (NIST) statistical tests
