Abstract:
Ultra-low power designs extensively exploit
the sub-threshold region of operation of Complementary
metal-oxide semiconductor (CMOS) circuits. Though sub-
threshold circuit operation shows huge potential towards
satisfying the ultra-low power requirement, increased
crosstalk and delay have become serious design challenges
particularly for sub-threshold interconnects. In this paper,
novel analytical time-domain models governing the output
voltage and crosstalk-induced delay of CMOS gates driv-
ing coupled resistive–capacitive interconnect in sub-
threshold domain are presented. Subsequently, the transient
analysis of simultaneously switching two and three coupled
interconnects is carried out. It is demonstrated that the
modeling of driver by linear resistance can lead to about
38 % average error in the estimation of propagation delay.
The numerical results illustrate that the proposed model
quite accurately estimates the performance of coupled on-
chip interconnects. An average error of less than 7 % is observed in estimation of waveform shape and delay.
