Abstract:
Planar copper interconnects suffer from surface roughness
that results in their performance degradation. In this paper, we
investigate the role of rough conductor surfaces on the
electrical performance of chip-to-chip interconnects using 3D
full wave simulation. Various interconnect performance
metrics, such as delay, energy-delay product, bandwidth
density, insertion loss and signal attenuation are evaluated
over broadband frequencies. Our results show that rough
conductor surfaces can significantly influence these metrics.
In that, the maximum penalty on insertion loss, attenuation,
delay, energy-delay product and bandwidth density is 50%,
86%, 3X, 3.7X and 28%, respectively. Finally, we report the
computational overhead for simulating high-speed
interconnects with rough surfaces
