Parametric modeling of high-speed coppergraphene interconnects and packages

Abstract

Demand for high-speed and miniaturized integrated circuits has resulted in increased power dissipation, transistor count and wiring density. While miniaturization in transistor sizes improve performance and power, scaling of interconnects result in degradation in their performance and electromigration reliability issues. Cu interconnects below 22nm technology node are unable to match the ITRS roadmap for interconnect technology. Copper core with graphene barrier can address the challenges faced by copper interconnects by lowering grain boundary scattering, surface scattering, increasing current density, activation energy, and providing parallel low resistance path for current conduction. Growth of graphene over Cu results in a larger grain size, which reduces the effective resistivity. Further, copper-graphene hybrid models reduce the size effect for a significant margin of interconnect dimensions. Ever-increasing demand for higher computational power, miniaturized transistor, and wiring size of interconnects lead to varying and uncertain design parameters, which can heavily affect the performance of electronics systems. These uncertainties and variability in design parameters arise due to fabrication processes, operating conditions, tolerances, and uncertain device behaviours. System response due to uncertain and variable parameters also becomes unpredictable and is characterized by a random process. The proper assessment of the output of such systems requires a detailed statistical analysis. Statistical analysis of electronics systems necessitates to perform design space exploration. Monte- Carlo is the standard way of doing design space exploration. Even though Monte-Carlo is accurate, it requires a high computational cost because of the involvement of a large amount of electromagnetic and SPICE simulations. When uncertain and variability parameters in design increase, the dimensionality of design space increases, leading to more time cost. Recently machine learning-based techniques have been extensively used in electronic packaging for the correct assessment of systems’ response. The advantage of machine learning over the conventional Monte-Carlo method is that it provides a surrogate model, which is later used to estimate the system response without running EM and SPICE simulation. Among the machine learning methods, artificial neural networks (ANNs), polynomial chaos (PC), and support vector machine (SVM) are pretty successful in electronic packaging applications. In this work, reliability assessment of copper-graphene hybrid on-chip interconnects is addressed using polynomial chaos method along with closed-form matrix rational approximation (MRA) model. The proposed approach will overcome EM and SPICE simulation challenges for any change in design parameters. This approach parameterize the rational transfer function with uncertain design parameters, temperature and dielectric surface roughness. Also, a surrogate model is developed for EM simulation, thus allowing the fast p.u.l parameter extraction for design space exploration problems. This thesis provides a comprehensive theoretical discussion together with several tutorial application examples, thus complementing the published material.