Abstract:
This paper presents an 8 × 2
7
-1 pseudo-random
binary sequence (PRBS) generator using Exclusive-OR (XOR)
gate merged D flip-flops. In the proposed architecture, to ensure
low power, a latch is removed from the D flip-flop and a
dynamic logic based XOR gate along with a clock signal is
used to get the functionality of master latch of the master-slave
D flip-flop. In the proposed architecture of XOR gate merged
D flip-flop, differential cascode voltage switch logic (DCVSL)
XOR gate is selected from dynamic logic which provides a
positive feedback (D-latch operation) in the pull-up network.
The PRBS generator, which is designed using the proposed
XOR gate merged D flip-flop, is designed in standard 65 nm
CMOS technology. The post-layout simulation results confirmed
the correct operation of the PRBS generator up to 2.56 Gb/s data
rate with 1 V supply. The proposed architecture shows the best
figure of merit compared to available PRBS generators in the
literature to the best of the author’s knowledge
