Abstract:
In this paper, a crossbar structure with CMOS based
memristor emulator is presented where the spacing between the
crossbar is modeled as per the memristor emulator circuit’s
area for a real-time design. The interconnect dimension in the
crossbar structure corresponds to 180 nm CMOS technology,
and the parasitics of the crossbar are extracted using ANSYS
Q3D extractor. The extracted parasitic components are used to
design a RC circuit model with the memristor emulator circuit to
analyze the signal delay for different states of the memristor and
crossbar sizes using the Cadence Virtuoso platform. The results
of the crossbar architecture provide an insight into how the signal
delay gets affected by the state of the memristor and with varying
the load capacitance present at the memristor crossbar array’s
output.
