Novel debug techniques and machine learning models to address gaps in conventional electrical validation of high-speed serial interface

Abstract

Design of high-performance integrated circuits is becoming cumbersome day by day due to shrinking technology and integration of heterogeneous blocks in a single SOC. Several issues arising due to complex architecture are discovered during Silicon validation that consists of testing (Wafer Testing, Automatic Test Equipment), digital validation (Functional Data path, FSM), analog bench validation (Electrical, Interoperability) and system validation. Each domain has its own flow, debug techniques and limitations. Analog validation focuses on electrical issues, which can pass through other design phases. Digital validation or other mentioned domain of post silicon alone is incapable of detecting electrical bugs because of the analog signal or due to mix signal nature of the IPs. So, analog bench validation has emerged as an important researched area. As we know in today’s era, high-speed serial interfaces are used in almost all silicon products. High-speed interface controller and PHY are used in communication system i.e. DDR, SATA, PCIe, USB, Ethernet, MIPI, HDMI etc., that use very high-speed data transfer rate with external devices. These are having purely analog behaviour and their failure is tough to be detected in any form of silicon validation. Also, it is difficult to analyse the signal integrity and mixed signal behaviour of these signals using techniques other than analog bench validation setup. These are related to one of the following unique families of noise sources: reflection (causes overshoots, undershoots, ringing noise, etc.), crosstalk between two or more nets (causes false trigger timing failure) and rail collapse (causes ground bounce, reduce noise margins). It is hard to detect issues which are purely based on signal integrity by digital validation. In this thesis, we discuss the research gaps in the area of high-speed serial interface in analog bench validation. Two important aspects related to high-speed serial interface designs are clock and detection of the devices at serial interface. Generally, every end user has faced device detection issues in some way e.g. while connecting USB3.0 pen drive, we observe that the speed of data transfer is lower by several orders of magnitude. In this thesis, we have tried to discuss and resolve the two major gaps related to PLL and device detection at serial interfaces. We have proposed a models to measure the signal integrity parameters of HSSI IPs. The proposed work highlights recent advances in analog bench validation with particular emphasis on high-speed serial interface. Further, technology updates pointing to future research directions for analog bench validation are summarized in this work. We have presented the impact of PLL locking on High-Speed Serial Interfaces for a 28 nm network SoC. The thesis also discusses associated debug challenges and techniques adapted to overcome these challenges and root-cause the problem. A novel dual register model is proposed to mitigate these failures. We also present a more accurate dual current model to mitigate the device detection failures. We report the models for measurement of de-embedded Signal Integrity parameters at High Speed Serial Interface. These models help in reducing the SI parameter computation time and also eliminate the need to purchase expensive equipment and de-embedding software.