INSTITUTIONAL DIGITAL REPOSITORY

Benchmarking of Analog/RF performance of Fin-FET, NW-FET, and NS-FET in the ultimate scaling limit

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dc.contributor.author Goel, A.
dc.contributor.author Rawat, A.
dc.contributor.author Rawat, B.
dc.date.accessioned 2022-06-02T13:44:33Z
dc.date.available 2022-06-02T13:44:33Z
dc.date.issued 2022-06-02
dc.identifier.uri http://localhost:8080/xmlui/handle/123456789/3477
dc.description.abstract In this work, we examine and benchmark the analog/RF performance metrics of silicon-based multigate devices, such as Fin-FET, gate-all-around nanowire (NW)-FET, and gate-all-around nanosheet (NS)-FET, in the ultimate scaling limit of sub-5-nm technology node. The performance analysis of multigate devices is done using a fully calibrated 3-D technology computer-aided design (TCAD) simulation based on self-consistent solutions of Poisson's equation, drift-diffusion transport equation, and carrier continuity equation with quantum correction terms for accounting band-to-band tunneling and confinement effects. Our performance benchmarking suggests that NS-FET with (100) surface orientation is a more favorable candidate over NW-FET and Fin-FET for analog/RF applications with higher voltage gain (32 V/V), higher peak cutoff frequency (373 GHz), and higher maximum oscillation frequency (389 GHz) at the 5-nm technology node. The performance benefits of NS-FET are found to be retained by decreasing the channel length, increasing the effective device width, and stacking the multichannel. Furthermore, our studies identify the proper directions to optimizations for achieving high-frequency and high-gain RF operations with multigate devices. en_US
dc.language.iso en_US en_US
dc.subject Analog/rf en_US
dc.subject Cutoff frequency en_US
dc.subject Fin-fet en_US
dc.subject Nanosheet (ns)-fet en_US
dc.subject Nanowire (nw)-fet en_US
dc.subject Si-based fet en_US
dc.subject Sub-5-nm technology node en_US
dc.subject Technology computer-aided design (tcad) simulation en_US
dc.subject Voltage gain en_US
dc.title Benchmarking of Analog/RF performance of Fin-FET, NW-FET, and NS-FET in the ultimate scaling limit en_US
dc.type Article en_US


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