Abstract:
There is a perpetual need of evolution in data converters to cater the demand of high speed and accurate data acquisition and processing. The trainable neural data converters can be trained using supervised learning techniques to produce precise data conversions. Such data converters are PVT immune and can be trained in real time using on-chip training signal generators. A trainable digital to analog converter needs accurate labeled analog signals as training signal. This paper proposes a CMOS-memristor hybrid training signal generator circuit and a memristive variable slope ramp generator circuit design. Proposed architecture is PVT immune and robust against mismatches and manufacturing imprecision in circuit component parameters. Proposed design is scalable to produce training signal for N-bit digital to analog converters. Proposed work is implemented and validated in standard CMOS 180nm technology node with SPICE model for the memristor.
