Abstract:
Post silicon analog validation and characterization refers to a set of activities done on a lab test bench setup to test and debug analog IPs in an SoC (System-on chip). An analog validation engineer typically uses a combination of hardware and software tools to validate an IP. Machine Learning (ML) as a tool has been successfully utilized by engineers in pre-silicon activities like highspeed channel modelling and Eye height/Width prediction. However, very limited research can be found regarding the use of ML algorithms in post silicon analog validation and characterization. Since, post silicon validation's main objective is to find out bugs in system, the accuracy to techniques used in test are of utmost importance. This paper investigates the use of ML in post silicon characterization. This has been done by taking an example use-case: computation of de-embedded signal integrity parameters (Eye Hight and Eye width) from non-de-embedded parameters in the characterization activity of high speed SERDES. It has been shown that by using ML algorithms, one can reduce the SI parameter computation timing with less than 2.1% average error.
