Abstract:
This paper proposes an inductor-less D-latch. In the proposed D-latch, negative feedback is used that makes input impedance appears to be inductive for the high-frequency input signal. The bandwidth is increased by around 23% due to this
efect. Two applications are shown in this paper to verify the proposed latch operation: a pseudo-random binary sequence
(PRBS) generator and a serializer. The speed of the PRBS generator and serializer has improved by 15.8% and 23% using
the proposed latch, respectively. The post-layout simulation results in 90 nm CMOS technology with a power supply of 1 V
prove the concept. To study functional correctness and scalability of the proposed architecture to lower technology nodes,
22 nm PTM model is used and verifed the correct operation of the proposed architecture.
