Abstract:
This paper proposes a quarter cycle update digital frequency locked loop for adverse single-phase grid systems. The proposed frequency locked loop is designed to obtain the grid estimates with-in a quarter cycle time of fundamental grid voltage input. It uses second order generalized integrator as a filter and orthogonal signal generator. Further a frequency locking stage is designed to estimate the frequency and phase angle using zero crossing detectors and digital counters. The proposed digital frequency locking stage works based on zero crossing instants of both in-phase and orthogonal phase of the input grid voltage corresponding to a two zero crossing and peak instant of the in-phase grid voltage to estimate the grid frequency and phase angle for every quarter cycle. The implementation of the proposed FLL is simple and has less computational overhead. The ability of the proposed FLL to track the frequency and phase under various steady-state (dc-offset and harmonics) and transient (frequency drift) grid disturbances is tested in simulation using MATLAB/SIMULINK, and the results are reported. The improved performance of the proposed method is verified by comparing it with the results of SOGI-FLL.
