Minimum DC voltage ripple switching sequence elicitation for dual inverter through AC load error volt-sec computation

Abstract

In voltage source inverters (VSI), the output voltage is synthesized in an average sense using pulsewidth modulation (PWM) techniques. In space vector PWM techniques, the average realization of the space vector using volt-sec balance results in an instantaneous error that influences the dc bus current. The instantaneous ac load error voltage maps onto the dc bus derive the dc bus current ripple signatures that would be useful to size the dc capacitor. Exploiting concept of instantaneous mapping of ac error voltage onto the dc bus through power factor axis coordinates, in this work, the unprecedented dc ripple voltage computational method is presented. The established synchronous power factor reference frame ensures accurate mapping of ac error voltage onto the dc bus and makes the computational method independent of sensing actual ac load current unlike conventional methods. With the eliminated actual load current dependence, the proposed model can predict the minimum dc voltage ripple yield switching sequence for VSIs at different loading conditions. The efficacy of the proposed model in terms of optimum switching sequence elicitation is demonstrated on the dual inverter configuration experimentally considering the inflated switching stress due to two inverter's switching.