Abstract:
Abstract:
This paper presents a pseudo-random binary sequence (PRBS) generator using merged XOR-D flip-flop as building blocks. The proposed architecture uses differential cascode voltage switch logic (DCVSL)-based dynamic XOR gate. The cross-coupled architecture of the pull-up network creating positive feedback in the DCVSL XOR gate is used as a latch by adding a transistor to apply a clock signal. This arrangement reduces the requirement of one latch in a master–slave D flip-flop (MS-DFF) from each lane. It reduces the area occupied in the layout and power requirements for the PRBS generator. The post-layout simulation for the PRBS generator operating at 5 Gb/s is performed in the 65 nm CMOS technology with a 1 V supply voltage. The proposed PRBS generator requires 2.4 mW of power. The jitter is 5.6 ps for the worst-case output of the proposed PRBS generator. In the proposed merged XOR-D flip-flop, there is an improvement of 33.3%, 27.4%, 29.1%, and 31.2% in power, area, maximum operating frequency, and the number of transistors, respectively, compared to when both XOR gate and D flip-flop are used separately. The figure of merit is improved by 14.8% for the proposed PRBS generator.
