Device-to-circuit Co-optimization of two-dimensional material-based field-effect transistors for future technology node

Abstract

Thequest fornewmaterialscapableof scalingbeyondthe limitsof siliconhas led totheemergenceoftwo-dimensionalmaterials(2DMs) inthedevicelandscape.Notably, 2DMs, suchasMoS2,WS2,BP, InSe, andothers, haveshownremarkableperformance andemergedasprominentcontendersforultra-scaledCMOSdevicesduetotheircarrier mobilitycomparable to silicon, ease of large-scale fabricationusingCMOS-compatible processingtechniques,andfeasibilityofthree-dimensional integration.Despitesignificant progress inthedevelopmentof2DM-basedfield-effecttransistors(FETs), theprocessing technology is still in its earlystages. As recent experimental progressunfolds, several pertinentquestionsarisebeforethedevelopmentofintegratedcircuits: (i)Howdoweselect thespecific2DMfromafamilyofover1800options?;(ii)Whatroledonon-idealities,such asinterfacetraps,highcontactresistance,andphononscattering,playindevice-to-circuit levelperformance?;and(iii)HowdotheycomparetoexistingSiCMOStechnology?.This thesisaimstoaddressthesequestionsthroughacomprehensivemodelingapproachthat encompassesdevice-to-circuitlevelanalysis. The main objective of this research is to undertake device-to-circuit level co-optimization of 2DM-FETs. To achieve this, a dissipative quantum transport simulation framework is developed to accurately estimate the performance of 2DM double-gate(DG)-FETs.Thequantumsimulationisconductedbyself-consistentlysolving the 2-DPoisson’s equationwithdiffusive non-equilibriumGreen’s function formalism (NEGF) under the self-consistentBornapproximationmethod. Using this developed framework, astudy isconductedonvarious2DM-FETs toevaluatetheir suitabilityfor digital applications at both the device and circuit levels. It is found thatmaterials withmoderatetransporteffectivemassandmoderatelyhightransversemassarebetter suited for digital logic applications. Subsequently, the quantumtransportmodeling frameworkisextendedtodescribetheinterfacetrapstatesinMoS2-FETsbyintroducing 0-Dstateswithabandgap.Theanalysisrevealsthatthetrap-inducedinelastictunneling currentstronglyaffectstheOFF-statecurrent, thresholdvoltage,andsubthresholdslope for gate lengthsbelow18nm,while charge trappingmarginally reduces theON-state current ofMoS2-FETs. Furthermore, awell-calibrated 3-DTCADtool is employed to thoroughly analyze andoptimize the performance of 2DMstackedgate-all-around nanosheet (NS)-FETs. The study indicates that single-layer (SL) and bilayer (BL) MoS2NS-FETsexhibitmorefavorableswitchingcharacteristicscomparedtoSiNS-FETs for sub-5nmnodes. Finally, CMOS inverters basedon2DMDG-FETs are explored and benchmarked against conventional Si-based devices. The study finds that the heterogeneousWSe2-MoS2CMOS inverter showsmore suitability for logicapplications withlargernoisemargins,nanowattpowerdissipation,andcomparativedelaytoSi-based inverter. Byaddressingtheseresearchobjectives,thisworkcontributestotheunderstanding andoptimizationof2DM-FETsatthedeviceandcircuit levels,pavingthewayfortheir potential integrationintofutureelectronicsystems.