Analysis and minimization of DC link ripple in voltage source inverters

Abstract

In voltage source inverters (VSIs), pulse width modulation(PWM) techniques are employed to convert the available DC voltage into AC voltage at a high switching frequency. In PWM techniques, the fundamental space vector is generated using the instantaneous volt-sec balance of the switching states. The difference between the fundamental space vector and instantaneous switching states creates the error voltage. This error voltage influences the DC bus current and load current ripple. The instantaneous projection of error voltage onto the DC bus gives the DC current ripple pattern. This current ripple pattern defines the DC bus voltage ripple. A novel minimum DC voltage ripple generating PWM selection algorithm is proposed in this work for a three-phase two-level voltage source inverter. To elicit the minimum DC voltage ripple, firstly, the DC capacitor current, DC voltage ripple, and DC source current ripple are mathematically modeled for a three-phase two-level VSI using an error voltage vector approach. Based on mathematical modeling, different continuous PWMs (CPWMs) and discontinuous PWMs (DPWMs) are compared to derive the minimum DC voltage ripple. After comparison, the minimum DC voltage ripple regions are identified for CPWMs and DPWMs in the modulation index (ma) and load angle (δ) plane. Based on the identified regions, an adaptive switching PWM selection algorithm is proposed to ensure the minimum DC voltage ripple irrespective of the load operating conditions. Further, by exploiting the concept of instantaneous mapping of AC error voltage onto the DC bus through power factor axis coordinates, in this research work, the unprecedented DC voltage ripple is modeled in the synchronous power factor reference frame for the dual inverter with common DC link. With the computed DC bus voltage ripple model, in this research work, the minimum DC voltage ripple yield PWM switching sequence is proposed for dual inverter with common DC link to minimize the DC bus voltage ripple for VSIs at different loading conditions. The effectiveness of the proposed work is demonstrated experimentally on a dual inverter setup in terms of optimum switching sequence elicitation. Further, the analysis of DC voltage ripple and DC source current ripple and its minimization is done on the dual inverter with a separate DC link. This work thoroughly analyzes the switching state correlation to minimize the DC voltage ripple without affecting the AC load current ripple. The analysis revealed that the switching algorithms must act to place the switching states by computing instantaneous DC capacitor current polarity. Using the polarity information, this work proposes the novel PWM dynamic sequencing mechanism that independently places the null and active vector in the sampling time interval to accomplish the minimum DC voltage ripple. Unlike conventional PWM methodologies, a prior capacitor current polarity computation makes the proposed algorithm dynamic in realizing the optimum switching sequence at any load condition without influencing the load current ripple. Further, the proposed method identifies the dwell times from the instantaneous phase reference voltages, freeing the algorithm from complex dwell time computations and sector identification. Therefore, the proposed methodology is simple in realizing variations in PWMs by simply shifting/segregating the null time. Further, it is demonstrated that discontinuous PWMs having low current ripple can yield the lowest voltage ripple with the proposed sequence; otherwise, it is the highest among all other PWM variants.