Abstract:
In today’s world, where many daily tasks rely on edge devices to process vast amounts
of data, there is a growing need for energy-efficient information processing. With the
limitations of CMOS technology scaling and the Von Neumann bottleneck becoming
apparent, researchers have shifted their focus towards developing new architectures,
methodologies, and devices that enable efficient computing while minimizing energy
consumption. Neuromorphic computing (NMC), inspired by the brain’s computational
efficiency, has gained attention as a promising approach for creating compact and
energy-efficient systems. This emerging field of neuromorphic computing explores ways
to implement biologically inspired systems in hardware.
The spiking neural network (SNN) resembles the simplified biological architecture
integrating neurons in the human brain where the information is processed in spikes.
The event-driven computing nature of SNN makes it inherently more bio-plausible and
energy-efficient than artificial neural networks (ANNs). This thesis describes the design
of the integrated circuits and systems for SNN realizing neuromorphic computing in
standard CMOS technology. Firstly, CMOS circuits of NMC’s building blocks were
implemented and then integrated to demonstrate pattern recognition application using
various architectures such as ANN, SNN, and associative memory.
Simulations and experiments were carried out to gain insights into CMOS circuits for the
development of real-time neuromorphic chip hardware. The entire circuit of ANN, SNN
and associative memory was designed at the transistor level, including CMOS circuits for
neurons, synapses, and synaptic crossbars. Training and inference results were evaluated
to ensure the accuracy of the implemented network. In addition to addressing image noise
in pattern recognition, challenges related to CMOS processes, such as PVT variations
and mismatches, were considered and analyzed.
The CMOS-based architectures proposed in this thesis for pattern recognition pave the
way for further research into neuromorphic computing systems using standard CMOS
technology in various cognitive applications.
